Method of semiconductor device having pads

专利摘要:
PURPOSE: A method for forming a semiconductor device having a pad is provided to be capable of minimizing pad etching effect due to a developing solution used when patterning a polyimide layer. CONSTITUTION: After preparing a semiconductor substrate(101) having a pad(106a), an etching stop layer(107) is formed on the entire surface of the resultant structure. A passivation layer(108) is formed at the upper portion of the etching stop layer. A passivation contact hole(109) is formed by selectively patterning the passivation layer for exposing the predetermined portion of the etching stop layer. A polyimide layer(110) is formed on the entire surface of the resultant structure. After forming a pre-pad hole by patterning the polyimide layer using a developing solution for exposing the predetermined portion of the etching stop layer, a pad hole(120) is formed by etching the etching stop layer exposed through the pre-pad hole for exposing the pad.
公开号:KR20030096887A
申请号:KR1020020033982
申请日:2002-06-18
公开日:2003-12-31
发明作者:최준영
申请人:삼성전자주식회사；
IPC主号:

专利说明:

Method of forming a semiconductor device having a pad {Method of semiconductor device having pads}
[3] The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device having a pad.
[4] Among the semiconductor devices, a pad plays a role of transmitting and receiving electrical signals between the inside and the outside of the semiconductor device. That is, the semiconductor device receives an operating voltage and an electrical signal for operation through a pad and outputs data through the pad. The pad is a part connected to the wire during a wire bonding process of an assembly process of forming a semiconductor chip.
[5] On the other hand, in general, a semiconductor device has double protective films for protecting the semiconductor device from an external harsh environment. Passivation layers and polyimide layers are the same. The passivation film is a protective film for protecting the semiconductor device from external environment such as moisture and pressure, and the polyimide film is a protective film for protecting the semiconductor device from high temperature, friction, radiation and chemicals. All of the above-described passivation layers undergo a patterning process for exposing the pads.
[6] 1 and 2 are cross-sectional views illustrating a method of forming a semiconductor device having a conventional pad.
[7] 1 and 2, an interlayer insulating film 2 is formed on a semiconductor substrate 1, and pads 3 are formed on the interlayer insulating film 2. The passivation film 4 is formed on the entire surface of the semiconductor substrate 1 having the pads 3. The passivation film 4 is patterned to form a passivation contact hole 5 exposing a predetermined region of the pad 3. The polyimide layer 6 is formed on the entire surface of the semiconductor substrate 1 including the inside of the passivation contact hole 5, and the polyimide layer 6 is patterned to expose the pads having been exposed to the passivation contact hole 5. 3) is exposed.
[8] The process of patterning the polyimide film 6 is briefly described. After the exposure process is selectively performed on the polyimide film 6, the developing process is performed. The developing process reacts the exposed polyimide film 6 with a developer solution to remove the exposed polyimide film 6. As a result, the pad 3 is exposed. In this case, the developer may etch the pad 3 formed of a metal film. As a result, the thickness of the pad 3 is reduced. As a result, a defect may occur in a wire bonding process in an assembly process for forming a semiconductor device into a semiconductor chip. The phenomenon in which the pads are etched by the developer may cause a misalignment during patterning of the polyimide film 3 to remove the patterned polyimide film 3, and then to form the polyid film 3 again. Can be further deepened during rework.
[9] SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of forming a semiconductor device capable of minimizing a phenomenon in which a developer used to pattern a polyimide film etches a pad.
[1] 1 and 2 are cross-sectional views illustrating a method of forming a semiconductor device having a conventional pad.
[2] 3 to 7 are cross-sectional views illustrating a method of forming a semiconductor device having a pad according to a preferred embodiment of the present invention.
[10] Provided are a method of forming a semiconductor device for solving the above technical problem. The method includes preparing a semiconductor substrate having a pad thereon. An etch stop layer is formed on the entire surface of the semiconductor substrate, and a passivation layer is formed on the etch stop layer. The passivation layer is patterned to form a passivation contact hole that exposes a predetermined region of the etch stop layer positioned on the pad. A polyimide film is formed on the entire surface of the semiconductor substrate including the passivation contact hole. The polyimide layer is patterned with a developer solution to form a preliminary pad hole exposing the etch stop layer exposed by the passivation contact hole. An etch stop layer exposed to the preliminary pad hole is etched to form a pad hole exposing the pad. In this case, the etch stop layer is formed of an insulating film having a slow etching rate due to the developer compared to the pad.
[11] Specifically, the etch stop layer is preferably formed of an insulating film having an etch selectivity with respect to the passivation film. The etch stop layer may be formed of at least one selected from a silicon nitride layer and an undoped amorphous silicon layer.
[12] Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the implementations introduced herein are provided so that the disclosure may be thorough and complete, and the spirit of the present invention will be fully conveyed to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. In addition, where a layer is said to be "on" another layer or substrate, it may be formed directly on the other layer or substrate, or a third layer may be interposed therebetween. Like numbers refer to like elements throughout the specification.
[13] 3 to 7 are cross-sectional views illustrating a method of forming a semiconductor device having a pad according to a preferred embodiment of the present invention.
[14] Referring to FIG. 3, a lower interlayer insulating film 102 is formed on a semiconductor substrate 101, and a buffer pattern 103 is formed on the lower interlayer insulating film 102. Although not shown, a transistor, a capacitor, a bit line, or the like necessary for the semiconductor device is formed before the lower interlayer insulating film 102 is formed. The lower interlayer insulating film 102 is preferably formed of a CVD silicon oxide film used as a general interlayer insulating film. The buffer pattern 103 is preferably formed of a conductive film, for example, a metal film. The upper interlayer insulating film 104 is formed on the semiconductor substrate 101 having the buffer pattern 103, and the upper interlayer insulating film 104 is selectively patterned to expose a predetermined region of the buffer pattern 103. The technical hole 105 is formed. The pad conductive layer 106 is formed on the entire surface of the semiconductor substrate 101 including the contact hole 105. The upper interlayer insulating film 104 is preferably formed of a CVD silicon oxide film used as a general interlayer insulating film. The pad conductive film 106 is preferably formed of a metal film which is a conductive film. For example, it is preferable to form with an aluminum film.
[15] Referring to FIG. 4, the pad conductive layer 106 is patterned to form a pad 106a. The pad 106a exchanges electrical signals between the inside and the outside of the semiconductor device. That is, the semiconductor device receives an operating voltage and an electrical signal for operation through a pad and outputs data through the pad.
[16] An etch stop layer 107 and a passivation layer 108 are sequentially formed on the entire surface of the semiconductor substrate 101 having the pads 106a. The etch stop layer 107 is formed of an insulating layer having a slower etch rate due to a developer solution used for patterning a general polyimide layer than the pad. In addition, the etch stop layer 107 may be formed of an insulating layer having an etch selectivity with respect to the passivation layer 108. The formation temperature of the etch stop layer 107 is preferably smaller than the melting point (melting point) of the pad 106a. The etch stop layer 107 may be formed of, for example, a nitride layer or an undoped amorphous silicon layer. The nitride layer may be formed of a silicon nitride layer (SiN) or a silicon oxynitride layer (SiON). have.
[17] The passivation film 108 may be formed of a PE enhanced oxide oxide and a silicon oxynitride layer that are sequentially stacked. In addition, the passivation film 108 may be formed of a PE silicon oxide film and a silicon nitride film sequentially stacked.
[18] 5, 6, and 7, the passivation layer 108 is patterned to form a passivation contact hole 109 exposing a predetermined region of the etch stop layer positioned on the pad 106a. The polyimide layer 110 is formed on the entire surface of the semiconductor substrate 101 including the inside of the passivation contact hole 109. The polyimide film 110 serves to protect the semiconductor device from external high temperature, friction, radiation, or various kinds of chemicals.
[19] A preliminary pad for selectively exposing the polyimide film 110 and removing the exposed polyimide film 110 with a developer to expose the etch stop layer 107 exposed to the passivation contact hole 109. The hole 115 is formed. In this case, the phenomenon in which the developer etches the pad 106a may be minimized due to the etch stop layer 107. As a result, defects occurring in the wire bonding process of the assembly process of forming the semiconductor element into the semiconductor chip can be minimized. In addition, when the polyimide film 110 is patterned, the phenomenon that the pad 106a is etched from the developer may be minimized even when misalignment occurs and rework is performed.
[20] Sidewalls of the preliminary pad holes 115 are formed as sidewalls of the polyimide layer 110 and the passivation contact hole 109.
[21] The etch stop layer 107 exposed in the preliminary pad hole 115 is etched until the pad 106a is exposed to form a pad hole 120 exposing the pad 106a. The sidewall of the pad hole 120 is formed of the polyimide film 110, the sidewall of the passivation contact hole 109, and the etch stop layer 107.
[22] As described above, according to the present invention, by forming an anti-etching film between the pad and the passivation film in electrical contact with the outside of the semiconductor device, the developer used when patterning the polyimide film, which is the final protective film of the semiconductor device Etching the pad can be minimized. As a result, defects in the assembly process caused by etching the pads from the developer can be minimized.

权利要求:
Claims (8)
[1" claim-type="Currently amended] Preparing a semiconductor substrate having pads thereon;
Forming an etch stop layer on the entire surface of the semiconductor substrate;
Forming a passivation layer on the etch stop layer;
Patterning the passivation layer to form a passivation contact hole exposing a predetermined region of the etch stop layer on the pad;
Forming a polyimide film on the entire surface of the semiconductor substrate including the passivation contact hole;
Patterning the polyimide layer with a developer solution to form a preliminary pad hole exposing the etch stop layer exposed to the passivation contact hole;
And etching the etch stop layer exposed to the preliminary pad hole to form a pad hole exposing the pad, wherein the etch stop layer is formed of an insulating film having a lower etch rate by the developer than the pad. Method of forming a semiconductor device.
[2" claim-type="Currently amended] The method of claim 1,
And the pad is formed of an aluminum film.
[3" claim-type="Currently amended] The method of claim 1,
And the etching preventing film is formed of an insulating film having an etching selectivity with respect to the passivation film.
[4" claim-type="Currently amended] The method of claim 1,
The etching prevention film is a semiconductor device forming method, characterized in that formed by the nitride film.
[5" claim-type="Currently amended] The method of claim 4, wherein
And the nitride film is formed of a silicon nitride film (SiN).
[6" claim-type="Currently amended] The method of claim 4, wherein
The nitride film is a silicon oxynitride film (SiON) formed method of forming a semiconductor device, characterized in that
[7" claim-type="Currently amended] The method of claim 1,
The etch stop layer is a semiconductor device forming method, characterized in that formed of an un-doped amorphous silicon layer (un-doped amorphous silicon layer).
[8" claim-type="Currently amended] The method of claim 1,
The passivation film is a semiconductor device forming method, characterized in that formed by the laminated (Plasma Enhanced silicon oxide) and nitride film.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
2002-06-18|Application filed by 삼성전자주식회사

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2002-06-18|Priority to KR1020020033982A

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2003-12-31|Publication of KR20030096887A

优先权:

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申请号 | 申请日 | 专利标题

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KR1020020033982A|KR20030096887A|2002-06-18|2002-06-18|Method of semiconductor device having pads|